|
|
Dec 05, 2024
|
|
ECE 5362 - Synthesis with Verilog HDL3 Credits (Minimum) 3 Credits (Maximum)
Logic synthesis with the Verilog hardware description language and commercial EDA tools. Includes an introduction to System Verilog. Project is required. Prer., ECE 4242/5242. Meets with ECE 4362.
Add to Portfolio (opens a new window)
|
|
|